So, I tried using an open-source toolchain for my next FPGA project. The first feature I checked in Yosys was SystemVerilog interfaces, but unfortunately, they were not supported. This presents a significant limitation in structuring a complex project effectively. Obviously, we need a framework to address this. MyHDL, Magma, and Chisel all sound promising, but who says I can’t create my own?
[Read More]GateForge Python RTL hardware design framework and RISC-V CPU
GitHub repo vagran/GateForge